A semiconductor packaging technology called chip scale package (“CSP”) is rapidly gaining popularity. In CSP technology, each chip is “rewired” connecting the electrodes on the chip to a matrix of solder bumps on a package surface. With this configuration, the semiconductor packaging is freed from the layout of the element electrodes arranged with narrow pitches on the semiconductor chip and can be made in a very compact size (almost the same size as the chip).
A technique in CSP, called a wafer level CSP process, is a manufacturing method by which semiconductor devices are fabricated without dicing the wafer into chips up to packaging. In wafer level CSP, the entire structure conventionally required for packaging, including solder bump terminal, is built across the wafer surface, that is, simultaneously for all the chips. The finished wafer, now having solder bumps across its surface, is diced to obtain the same packaged semiconductor devices as conventional ones.
The chips fabricated on a semiconductor wafer in wafer level CSP are cut physically into individual chips, for example, with a dicing device. See, for example, non-patent document 1.
FIG. 10 illustrates a wafer level CSP manufacturing method, showing individual steps in (a) to (f). Referring to (a) and (b) of FIG. 10, first of all, posts 83 are formed on a semiconductor wafer 81 to allow wires to be drawn from aluminum electrodes 82 on the semiconductor wafer 81. Then, the semiconductor wafer 81 is sealed with resin 84 as shown in (c) of FIG. 10. Next, as in (d) of FIG. 10, terminals 85 are provided on the seal resin 84 so as to connect to the posts 83. Thereafter, the semiconductor wafer 81 is diced with a dicing device 86 as shown in (e) of FIG. 10, to obtain individual chips 87 shown in (f) of FIG. 10.
The illustrated method provides no protection film on the side faces of the packages in structural design, making the wafer level CSPs vulnerable to mechanical impact. This problem is addressed, for example, in patent document 1 by forming a protective resin layer on the side faces of the wafer level CSPs for reinforcement.
As would be understood from the description above, the wafer level CSPs are vulnerable to mechanical impact and could be damaged when cut into individual packages in manufacture. For example, external parts of the packages may break away or crack. If the damage is critical, it will seriously affect chip circuitry and be detected later by inspection. On the other hand, if the damage is of a minor nature and does not affect the circuitry, it will not be detected. Nevertheless, even minor damage can spread under thermal or impact-induced stress after the package is mounted on a circuit board and potentially affect circuit operation. Therefore, it is desirable if minor damage can be detected in inspection.
FIG. 12 is a block diagram of a conventional semiconductor device 90. A semiconductor device 90 includes a semiconductor chip 92. An electric line 93 is formed along the periphery of the semiconductor chip 92 for damage detection. An end of the electric line 93 is provided with a detection signal input terminal 94 to which is supplied a detection signal with which a break in the electric line 93 is detected. The other end of the electric line 93 is provided with an output terminal 95 from which the detection signal having passed through the electric line 93 is output.
As voltage is applied to the detection signal input terminal 94, electric current having passed through the electric line 93 is detected at the output terminal 95. If the semiconductor chip 92 is damaged and the electric line 93 is broken, no current is detected at the output terminal 95, which enables detection of damage to the semiconductor chip 92.
Patent document 2, as an example, discloses a similar chip damage detection method. According to the method, an electric line is formed along the periphery of the chip, and damage detection probe pads are formed on both ends of the line. However, the structure requires the provision of the two new measurement terminals to detect damage to the peripheral part of the chip. The increased chip area presents a new problem.
Some documents disclose chip damage detection structures which require no new measurement terminals. Patent document 3 discloses a structure in which only one detection terminal is needed. Meanwhile, patent document 4 discloses a structure in which a wire is connected to an existent terminal via an internal circuit. The terminal is used for inspection only during testing. The structure hence needs no additional measurement terminals.
Patent documents 5 to 7 disclose chip heating technology using a circuit in a semiconductor device.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-138245 (Tokukai 2000-138245; published May 16, 2000)
[Patent Document 2]
Japanese Unexamined Patent Publication No. 7-193108/1995 (Tokukaihei 7-193108; published Jul. 28, 1995)
[Patent Document 3]
Japanese Unexamined Patent Publication No. 5-95039/1993 (Tokukaihei 5-95039; published Apr. 16, 1993)
[Patent Document 4]
Japanese Unexamined Patent Publication No. 2005-277338 (Tokukai 2005-277338; published Oct. 6, 2005)
[Patent Document 5]
Japanese Unexamined Patent Publication No. 2002-26232 (Tokukai 2002-26232; published Jan. 25, 2002)
[Patent Document 6]
Japanese Unexamined Patent Publication No. 6-97245/1994 (Tokukaihei 6-97245; published Apr. 8, 1994)
[Patent Document 7]
Japanese Unexamined Patent Publication No. 2005-172467 (Tokukai 2005-172467; published Jun. 30, 2005)
[Non-patent Document 1]
Wafer Level CSP by Masumoto, et al., Fujikura Technical Letter, page 77 to page 80, Issue 99, October 2000